Electrostatic Discharge (ESD) events are a common issue in semiconductor devices. For example, an ESD event to one or more pins of an integrated circuit package can damage or destroy the semiconductor device. More specifically, ESD-related failures can be exhibited in a number of ways such as, for example, junction leakage, short, or burn-out; dielectric rupture; resistor-metal interface rupture; and resistor/metal fusing, to name a few. These failures are especially true in sensitive devices such as, for example, a MOS device which has thin gate oxides.
There are three predominant ESD models for integrated circuits. These models include the Human Body Model (HBM), the Charged Device Model (CDM), and the Machine Model (MM). The HBM simulates the ESD event when a person charged to a positive potential or negative potential contacts an integrated circuit which is at a different potential. The CDM, on the other hand, simulates the ESD event that occurs when a device charges to a certain potential, and contacts with a conductive surface at a different potential. The MM simulates the ESD event that occurs when a part of an equipment or tool comes into contact with a device at a different potential.
To prevent ESD occurrences, ESD devices are formed with and connected to semiconductor devices in order to protect the devices. The ESD devices operate to absorb an electrostatic discharge and bring it to ground to avoid damage to or destruction of the semiconductor device. However, ESD devices are typically very large devices that utilize valuable space on a chip. In current technology, this poses an issue since such chip space is at a premium, especially in 90 nm nodes and less. Also, known ESD devices have a tendency to fail due to thin underpass connection during ESD events.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.